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# Introduction to PLL of LPC2148

Updated: Mar 12, 2022

The PLL is used to multiply oscillator frequency or clock coming from an external source. There are two on chip PLL modules available in LPC2148 : The PLL0 and PLL1. The PLL accept an input clock frequency in the range of 10 MHz to 25 MHz only.

The input frequency is multiplied up to the range of 10 MHz to 60 MHz for the CCLK and 48 MHz for the USB clock using a Current Controlled Oscillator (CCO). In this tutorial I will explain how to configure the PLL to generate a desired output frequency. The PLL multiplier can be an integer value from 1 to 32. The frequency of the CCO (current control oscillator of the PLL must be with in 150 to 320 MHz). There is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency.

The divider may be set to divide by 1, 2, 4, or 8 to produce the output clock.

Basic Notations:

Fosc : Input frequency to the PLL

Fo: PLL output clock

Fcco : CCO frequency of the PLL

M : PLL Multiplier

P : PLL Divider

Possible values of M : 1 to 32

Possible value of P : 1, 2 , 4 , 8

Fo = M*Fosc

Fcco = Fosc*M*2*P

Fcco = Fo*2*P

Fo : 10 MHz to 60 MHz

Fcco : 150 MHz to 320 MHz

PLL configuration example:

Objective:

To Determine values of M and P to generate 60 MHz clock if Fosc is 10 MHz.

Step1: Determine value of M

Here Fo: 60 MHz, Fosc : 10 MHz

M = 60/10 = 6

Step 2: Determine P

Pmin = 150/(2*Fo) = 1.3

Pmax = 320/(2*Fo) = 2.6

1.3<p<2.6 so the possible value of the P will be: 2

In the next tutorial we will explore the registers of the PLL and programming.